KSC Single Chip Emulator

KSC-Hardware Because of increasing complexity of 8 and 16 bit processor applications, development tools have to meet higher demands. In particular the testing of complex applications with a real time trace facility requires an effective debugger.
The KSC Single Chip Emulator with its broad range of performance, functionality and technology is well suited to solve the hardest problem. It is a flexible system, easily ported to different processors within the same family.

The KSC hardware features a large number of events with corresponding width, which are also useable also as breakpoints. They are controlled by a 16 level sequencer. An efficient trace memory records all processes and presents them in a variety of formats.

The emulator is easy and friendly to use with the KSC VISION interface. Many windows can be adjusted individually and a context-sensitive help system is provided.

KSC Hardware

Simulation memory
64 KB RAM program (extendable to 256 KB or 1 MB), 64 KB XData (in case of the X52 XData may be read out during emulation without loss of realtime functionality), mapping between target system and emulator is possible in 256 byte increments for the first 64 KB and in 4 KB increments above 64 KB. Program and data memory may be combined with the X52 (Von-Neumann-architecture).

Trigger logic
Eight hardware trigger with 80 bit width for address- and data buses, ports, control lines and 8 external input probes.

Trigger and break logic
Each of the 8 hardware triggers may be used as a breakpoint; additionally up to 128.000 address-breakpoints, break during trace full and after a timeout. Instead of break a snapshot (short stop, window update and restart) may be set.

Tag memory
4 bits for trigger/breaks and for recording of memory accesses are assigned to each address accessable by the processor. When using simulation memory expansion 256 Ktag-bits at 64 KB / 1 Mtag-bits at 256 KB / 4 Mtag-bits at 1 MB are also available. They are also usable as address breakpoints. Breakpoints are set by clicking on the appropriate line in the disassembly or source window. Each access to each external memory address is recorded.

Sequencer
Flexible processing of the 8 triggers and the tag events with 4 counters (1-65000) in a 16 level sequencer for:

  • Trigger output
  • Break
  • Snapshot
  • Time measurement
  • Event counter
  • Branching into another level
  • Trace qualification
  • Trace trigger
  • Trace control (on/off)
On each level, individual break and trace options may be set. Each level may consist of several sub-levels, with parallel processing of all definitions within each the level. Clear presentation by C-like syntax.

External input/output probes
8 external input probes for trigger, break and trace. A signal, i.e. for addressing the oscillator, is created at the external output probe upon reaching 6 out of 8 trigger points.

Time measurement (2) /Event counter (1)

  • 40 bit timer (resolution: 100ns), start/stop by 2 triggers or external, online analysis of minimum, maximum or total time measurement between start/stop triggers
  • 40 bit timer for CPU-cycles or assembler commands
  • 40 bit counter for measurement of variable events

Code coverage
By complete recording of all external CPU memory accesses perfect code coverage is ensured and presented in the disassembly or source window by highlighted areas or symbols.

Trace analyser

  • Trace option with more than 16.000 samples with 80 bit width for address-, data-, control bus, ports, and 8 external output probes, 16 bit for time measurement between the samples (resolution: 100 ns - 5 ms)
  • Trace qualifier: recording of elected processor cycles like read, write, execute, first byte of command, start of HLL line, special address range
  • Trace trigger: interrupt of trace recording when reaching the trace trigger without stopping the processor
  • Range trace (for defined address ranges)
  • Variable selection of pre- and post-trigger recording
  • Trace qualification and trace trigger are controlled by the sequencer
  • Presentation of trace recording as processor status, disassembled or in HLL formats
  • Data qualification
  • Data filtering
  • Time measurement between various samples (absolutely from a fixed point or relative between successive samples)
  • Trace recording may be stored and loaded in different forms as a data set

Interfaces
RS232C (COM 1-4), max. 115 Kbaud, parallel interface (LPT 1-3) of any PC (default).

Technical data
Supply: 40 W, 110/240 VAC
Ambient operating temperature: 0°C to 35°C
Weight: ca. 4 kg
Housing dimensions (HxWxD): 108 x 258 x 312 mm, without cable
CE-compliant

Target adaptation
For the connection to the target system, adapters for DIL, SDIP, PLCC, MQFP and TQFP (with up to 0,5 mm pitch) packages are available.